Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a fuse circuit in which an address corresponding to a repair target memory cell is programmed.
In general, a semiconductor memory device including a double data rate synchronous DRAM (DDR SDRAM) is provided with a large number of memory cells. As fabrication technologies have developed, the integration density of the semiconductor memory device gradually increases and the number of memory cells also gradually increases. When a fail occurs in any one of the memory cells, a corresponding semiconductor memory device may not perform a desired operation and thus may be discarded as a bad product. As fabrication technologies for semiconductor memory devices have advanced, a fail may occur in a few memory cells. If an entire semiconductor memory device is discarded as a bad product due to such fails, it may be inefficient in terms of the yield of products. In order to address such a concern, redundancy memory cells as well as normal memory cells are provided within a semiconductor memory device. When a fail occurs in a normal memory cell, it is replaced with a redundancy memory cell. A failed normal memory cell which is to be replaced with a redundancy memory cell may be referred to as a “repair target memory cell.”
Meanwhile, a semiconductor memory device includes a fuse circuit which can program an address corresponding to a repair target memory cell (hereinafter, referred to as a repair target address). A programming refers to a series of operations for storing a repair target address in a fuse circuit.
In general, a fuse circuit includes a plurality of fuses. Representative methods for programming such fuses include a laser cutting method and an electrical cutting method. According to the laser cutting method, a cutting target fuse corresponding to a repair target address is blown and cut by a laser beam. According to the electrical cutting method, a cutting target fuse is melted and cut by applying an over-current thereto. The laser cutting method may be performed at a wafer level which is prior to a package level of a semiconductor memory device, and the electric cutting method may performed at a package level. Since the laser cutting method is simpler than the electrical cutting method, it is widely used. However, the electrical cutting method is also widely used because it can be used even after the packaging step.
As described above, the address corresponding to the repair target memory cell is programmed in the fuse circuit. That is, the repair target address is programmed in the fuse provided in the fuse circuit, and the semiconductor memory device performs the repair operation by using the repair target address. In other words, when an external address is for accessing the repair target memory cell, the semiconductor memory device compares the external address with the repair target address, and performs the repair operation to access the redundancy memory cell instead of the repair target memory cell according to the comparison result.
FIG. 1 is a diagram illustrating a conventional fuse set. As described below, a fuse circuit includes a plurality of fuse sets.
Referring to FIG. 1, the fuse set includes an enable fuse unit 110, zeroth to k-th fuse units 120 (where k is a natural number), and a fuse information summation unit 130.
The enable fuse unit 110 is configured to generate information indicating that repair target addresses are programmed in the zeroth to k-th fuse units 120. A logic level value of a fuse enable signal F#EN is determined according to whether or not an enable fuse F is cut. For reference, the enable fuse unit 110 receives a power-up signal PWR which is activated when an external power supply voltage VDD applied to the semiconductor memory device is higher than a certain voltage level.
The zeroth to k-th fuse units 120 are configured to compare the repair target addresses programmed in the respective fuse units with zeroth to k-th external addresses ADD#0, ADD#1, . . . , ADD#K, and generate zeroth to k-th address comparison signals F_ADD#0, F_ADD#1, . . . , F_ADD#K. The zeroth to kith fuse units 120 output the zeroth to k-th external addresses ADD#0, ADD#1, . . . , ADD#K as the zeroth to k-th address comparison signals F_ADD#0, F_ADD#1, . . . , F_ADD#K, or output the zeroth to k-th address comparison signals F_ADD#0, F_ADD#1, . . . , F_ADD#K by inverting the zeroth to k-th external addresses ADD#0, ADD#1, . . . , ADD#K, according to the repair target addresses programmed in the respective fuse units.
For convenience of explanation, a detailed circuit diagram of the k-th fuse unit 121 is illustrated in FIG. 1. The k-th fuse unit 121 outputs the k-th external address ADD#K as the k-th address comparison signal F_ADD#K, or outputs the k-th address comparison signal F_ADD#K by inverting the k-th external address ADD#K, according to whether or not a k-th address fuse F#K is cut.
The fuse information summation unit 130 is configured to sum the zeroth to k-th address comparison signals F_ADD#0, F_ADD#1, . . . , F_ADD#K, and generate a repair detection signal HITB. The repair detection signal HITB is activated when all of the zeroth to k-th address comparison signals F_ADD#0, F_ADD#1, . . . , F_ADD#K are activated because the repair target addresses programmed in the respective fuses of the zeroth to k-th fuse units 120 are equal to the zeroth to k-th external addresses ADD#0, ADD#1, . . . , ADD#K in such a state that the fuse enable signal F#EN is activated by the enable fuse F.
FIG. 2 is a block diagram illustrating a partial configuration of the semiconductor memory device including the fuse set of FIG. 1.
Referring to FIG. 2, the semiconductor memory device includes a repair control signal generation unit 210 and an address decoding unit 220.
The repair control signal generation unit 210 is configured to compare the repair target addresses programmed in the respective fuses with the zeroth to k-th external addresses ADD#<0:K>, and generate a repair control signal NXE. The repair control signal generation unit 210 includes a plurality of fuse sets 211 and a control signal output section 212.
The plurality of fuse sets 211 includes first to nth up fuse sets 211_U1, 211_U2, . . . , 211_Un and first to nth down fuse sets 211_D1, 211_D2, . . . , 211_Dn (where n is a natural number). The first to nth up fuse sets 211_U1, 211_U2, . . . , 211_Un and the first to nth down fuse sets 211_D1, 211_D2, . . . , 211_Dn have the structure of FIG. 1. The first to nth up fuse sets 211_U1, 211_U2, . . . , 211_Un and the first to nth down fuse sets 211_D1, 211_D2, . . . , 211_Dn are configured to compare the repair target addresses programmed in the respective fuse sets 211 with the zeroth to k-th external addresses ADD#<0:7>, and output first to nth up repair detection signals HITB_U#<1:n> and first to nth down repair detection signals HITB_D#<1:n>.
The control signal output section 212 is configured to receive the first to nth up repair detection signals HITB_U#<1:n> and the first to nth down repair detection signals HITB_D#<1:n>, and output the repair control signal NXE. The repair control signal NXE is activated when any one of the first to nth up repair detection signals HITB_U#<1:n> and the first to nth down repair detection signals HITB_D#<1:n>. That is, the repair control signal NXE is activated when the inputted zeroth to k-th external addresses ADD#<0:K> correspond to the repair target addresses.
The address decoding unit 220 is configured to decode the zeroth to k-th external addresses ADD#<0:K> to access normal memory cells or redundancy memory cells corresponding to the zeroth to k-th external addresses ADD#<0:K> under the control of the repair control signal NXE and an internal active signal BACT. The address decoding unit 220 includes first to nth up address decoding sections 220_U1, 220_U2, . . . , 220_Un and first to nth down address decoding sections 220_D1, 220_, . . . , 220_. The first to nth up address decoding sections 220_U1, 220_U2, . . . , 220_Un and the first to nth down address decoding sections 220_D1, 220_D2, . . . , 220_Dn can determine whether the inputted zeroth to k-th external addresses ADD#<0:K> correspond to the repair target memory cells in response to the repair control signal NXE, and control the normal memory cells or the redundancy memory cells to be accessed in response to the activation timing of the internal active signal BACT.
FIG. 3 is a timing diagram illustrating the circuit operation of the semiconductor memory device shown in FIG. 2.
Referring to FIG. 3, the zeroth to k-th external addresses ADD#<0:K> are inputted from the exterior in response to an active command ACT. At this time, normal addresses ADD_NOR corresponding to the normal memory cells or repair target addresses ADD_RED corresponding to the repair target memory cells may be inputted as the zeroth to k-th external addresses ADD#<0:K>. The zeroth to k-th external addresses ADD#<0:K> are inputted to the first to nth up fuse sets 211_U1, 211_U2, . . . , 211_Un and the first to nth down fuse sets 211_D1, 211_D2, . . . , 211_Dn of the repair control signal generation unit 210. The first to nth up fuse sets 211_U1, 211_U2, . . . , 211_Un and the first to nth down fuse sets 211_D1, 211_D2, . . . , 211_Dn compare the repair target addresses programmed in the respective fuses with the zeroth to k-th external addresses ADD#<0:K>, and activate the corresponding repair detection signals among the first to nth up repair detection signals HITB_U#<1:n> and the first to nth down repair detection signals HITB_D#<1:n>. Accordingly, the repair control signal NXE is activated. In FIG. 3, “tA” represents a time taken until the repair control signal NXE is generated after the zeroth to k-th external addresses ADD#<0:K> are inputted in response to the active command ACT.
As described in FIG. 3, the repair control signal NXE may have a logic high level or a logic low level. When the repair control signal NXE is at a logic high level, the zeroth to k-th external addresses ADD#<0:K> may correspond to the normal memory cells. When the repair control signal NXE is at a logic low level, the zeroth to k-th external addresses ADD#<0:K> may correspond to the repair target memory cells. When the repair control signal NXE is at a logic low level, that is, the zeroth to k-th external addresses ADD#<0:K> correspond to the repair target memory cells, the redundancy memory cells are accessed, instead of the normal memory cells.
The internal active signal BACT is a signal generated by delaying the active command ACT by a predetermined time. The internal active signal BACT controls an operation timing when the normal memory cells or the redundancy memory cells are accessed by the address decoding unit 220. As described in FIG. 3, the internal active signal BACT is to change from a logic low level to a logic high level after a state in which the repair control signal NXE is determined to a logic high level or a logic low level. The address decoding unit 230 controls the normal memory cells or the redundancy memory cells to be accessed in response to the internal active signal BACT which changes in the above-described manner. In FIG. 3, “tB” represents a time taken until the internal active signal BACT is activated after the active command ACT is inputted.
As described above, the internal active signal BACT is to be activated after the state in which the repair control signal NXE maintains a preset logic level value. The repair control signal NXE and the internal active signal BACT is a signal in which an asynchronous delay time is reflected. The repair control signal NXE is a signal in which the delay time tA corresponding to the circuit operation of the repair control signal generation unit 210 is reflected after the zeroth to k-th external addresses ADD#<0:K> are inputted, and the internal active signal BACT is a signal in which the delay time tB predetermined from the input of the active command ACT is reflected. In other words, the internal active signal BACT is desired to be activated after the repair control signal NXE is activated. That is, the delay time tA reflected in the repair control signal NXE is to also be reflected in the delay time tB from the input of the active command ACT to the generation of the internal active signal BACT.
The conventional semiconductor memory device does not have a test operation mode for measuring the delay time tB of the internal active signal BACT. Therefore, the delay time tB is estimated by an indirect method through a test operation mode for other purpose. Such a test operation mode is performed several times. In this manner, the delay time tB of the internal active signal BACT is determined. However, a relatively long test time is taken until a desired measurement value is obtained through such a test operation mode. Furthermore, since the reliability of the obtained measurement value is low, the activation timing of the internal active signal BACT is set to have a sufficient margin by further adding a time margin for a stable operation to the obtained measurement value. However, since such a method substantially delays the activation timing of the internal active signal BACT, the data access speed of the semiconductor memory device is lowered. Therefore, there is a demand for a circuit which more quickly and more accurately measures the delay time tB for which the active command ACT is delayed to generate the internal active signal BACT.